Our client is an exciting Bristol based (South West) is looking for a top-quality IC Layout engineer, skilled in Physical implementation, to support the analogue infrastructure, physical design, sign-off and bring-up of future devices built using the world's most advanced CMOS processes.

A strong degree (1st/2:1) from a top-tier University is required, with experience in design and implementation of high performance, low power chips from RTL delivery through to GDSII.

Depending on the experience level, applicants for the role of Physical IC Design Engineer / IC Layout would benefit from experience in some or all of the following areas:

*CMOS digital chip design and implementation.
*Design automation and analysis using scripting languages, particular Tcl and Perl.
*Block build flows and the EDA tools to support them, in particular tools from Magma and Synopsys.
*Sign-off methodology and EDA tools for TA, Noise, Power, etc.
*Architecture and physical implementation of high performance clock distribution for advanced CMOS
*Structured design styles involving placed gates.
*ATPG tools and methodologies.
*Bringup and testing of devices in the laboratory and production test houses

For further information on the role of Physical IC Design Engineer / IC Layout please contact Guy Brown on gbrown@redlineplc.Com or call +44 1582 878807 (quoting ref GB-10139/30)

Contact details

• Email: GBrown@redlineplc.com
• Phone: 01582 450054